I/O-intensive processing with POWER9-based systems

H. Peter Hofstee
Speaker: H. Peter Hofstee, PhD
Distinguished Research Staff Member, IBM Austin Research Laboratory
Professor in Big Data Systems at Delft University of Technology
Location: Rudder Tower 504
Time: October 29, 2018 - 3:00-4:00pm


While the rate of performance improvement for general-purpose processors has slowed, performance at the system level continues to grow at a fast pace, enabled by new storage, memory, and interconnect technologies, and by architectures combining POWER9 with NVIDIA GPUs and Xilinx FPGAs that are more specialized towards new workloads such as AI and analytics. In this talk we will review some of the bandwidth trends in particular, and discuss a set of POWER9-based systems with unprecedented levels of bandwidth. We discuss how these systems are leveraged in a number of high-bandwidth applications, ranging from HPC and AI to in-memory databases.

Speaker's Bio

Peter Hofstee is a Dutch physicist and computer scientist who currently is a distinguished research staff member at the IBM Austin Research Laboratory, USA, and a part-time professor in Big Data Systems at Delft University of Technology, Netherlands. Hofstee is best known for his contributions to Heterogeneous computing as the chief architect of the Synergistic Processor Elements in the Cell Broadband Engine processor used in the Sony Playstation3, and the first supercomputer to reach sustained Petaflop operation. After returning to IBM research in 2011 he has focused on optimizing the system roadmap for big data, analytics, and cloud, including the use of accelerated compute. His early research work on coherently attached reconfigurable acceleration on POWER7 paved the way for the new coherent attach processor interface on POWER8. Hofstee is an IBM Master Inventor with more than 100 issued patents and a member of the IBM Academy of Technology. (Peter Hofstee at Wikipedia)